1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a semiconductor integrated circuit laid out in accordance with a standard cell system.
2. Description of Related Art
Recently, when a semiconductor integrated circuit is designed, a so called standard cell system is used as a layout method. In brief, a number of standard cells having various logic functions are previously prepared, and the standard cells are located in accordance with a designed logic circuit, so that a standard cell array is formed. Furthermore, a plurality of standard cell arrays thus formed are located, and then, interconnections for ordinary signals supplied to the standard cell arrays and/or transferred between the standard cell arrays, and interconnections for clock signals supplied to the logic circuits, are laid out.
Now, a method for designing a semiconductor integrated circuit in accordance with a conventional standard cell system will be described with reference to FIG. 5.
As shown in FIG. 5, a plurality of standard cell arrays 9, 10 and 11 are located in accordance with a designed logic circuit. Each of the standard cell arrays 9, 10 and 11 has terminals for a clock signal provided on one side thereof and terminals for an ordinary signal provided on a side thereof opposite to the first mentioned side. For example, the standard cell array 9 includes terminals T1 for a clock signal and terminals T4 for an ordinary signal.
In addition, a clock signal interconnection 12 to be connected to the terminals on the respective side of these standard cell arrays, and an ordinary signal interconnection 13 for transferring the ordinary signals between the standard cell arrays, are located, and connected to necessary terminals provided on the sides of the standard cell arrays.
Now, this will be explained in detail with reference to FIG. 6. FIG. 6 is a diagrammatic plan view of one standard cell 14 included in the standard cell array 9, and connected to the clock signal interconnection 12 and the ordinary signal interconnection 13. The content of the standard cell is various and different from one standard cell to another. The shown example is a standard cell including two transistors receiving a clock signal and an ordinary signal.
As shown in FIG. 6, the clock signal interconnection 12 is connected to the standard cell 14 at the terminal T1 positioned at an upper side of the standard cell in the drawing. On the other hand, the ordinary signal interconnection 13 is connected to the standard cell 14 at the terminal T4 positioned at a lower side of the standard cell in the drawing.
Since there is possibility that each of the clock signal interconnection 12 and the ordinary signal interconnection 13 exists on both opposite sides of the standard cell array, the standard cell has the clock signal terminal T1 and an ordinary signal terminal T2 provided on the upper side of the standard cell and a clock signal terminal T3 and the ordinary signal terminal T4 provided on the lower side of the standard cell. However, all of the terminals T1 to T4 were never used without exception. For example, in the example shown in FIG. 6, the terminals T2 and T3 are not used.
However, when the standard cell as shown in FIG. 6 is used, the following problem has been encountered.
Namely, in the standard cell, a clock is supplied from the clock signal terminal T1 through an internal interconnection 15a to an internal element, for example, a transistor. In this case, the terminal T3 is not used. The clock signal is supplied from the internal interconnection 15a through contacts to an interconnection of another level. However, an interconnection portion 15b between a contact C1 and the terminal T3 is of no use at all.
This useless interconnection 15b exists in each of the standard cells. The useless interconnection becomes a considerable amount for each of the standard cell arrays. This means that the clock signal interconnection 12 meaninglessly includes an excessive parasitic capacitance. Therefore, if the conventional standard cells are used, unnecessary parasitic capacitance is generated, with the result that a speeding-up of a circuit operation is obstructed, and a clock skew occurs.